A low-complexity fetch architecture for high-performance superscalar processors

Autor:	Josep L. Larriba-Pey, Alex Ramirez, Mateo Valero, Oliverio J. Santana
Rok vydání:	2004
Předmět:	Computer science Fetch Parallel computing Branch predictor Low complexity Computer architecture Hardware and Architecture Superscalar Key (cryptography) Parallelism (grammar) Code (cryptography) Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING Architecture Software Information Systems
Zdroj:	ACM Transactions on Architecture and Code Optimization. 1:220-245
ISSN:	1544-3973 1544-3566
DOI:	10.1145/1011528.1011532
Popis:	Fetch engine performance is a key topic in superscalar processors, since it limits the instruction-level parallelism that can be exploited by the execution core. In the search of high performance, the fetch engine has evolved toward more efficient designs, but its complexity has also increased.In this paper, we present the stream fetch engine, a novel architecture based on the execution of long streams of sequential instructions, taking maximum advantage of code layout optimizations. We describe our design in detail, showing that it achieves high fetch performance, while requiring less complexity than other state-of-the-art fetch architectures.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::54ab7d6ffdaf40664528164c81f57e70 https://doi.org/10.1145/1011528.1011532 Zobrazit plný text záznamu