Fault and Soft Error Tolerant Delay-Locked Loop
| Autor: | Jun-Yu Yang, Shi-Yu Huang |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Phase-locked loop
Soft error Control theory Computer science Delay-locked loop 0202 electrical engineering electronic engineering information engineering Redundancy (engineering) 02 engineering and technology Fault (power engineering) Chip Synchronization Clock synchronization 020202 computer hardware & architecture |
| Zdroj: | ATS |
| Popis: | We present in this paper the first fault and soft error tolerant Delay-Locked Loop (DLL) design, useful for the clock synchronization in a chip incorporating heterogeneous functional dies. In this robust DLL design, we introduce a powerful timing correction scheme to remedy the timing shortfall in a naive Triple-Module Redundancy (TMR) architecture. Post-layout simulation results using a 90nm CMOS process is used to verify the performance of this design. In addition to the tolerance of randomly injected faults or soft errors, the Maximum Phase-Error can be improved tremendously from 117ps to just 17ps by the proposed timing correction scheme. |
| Databáze: | OpenAIRE |
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