| Autor: |
Jung-Hoon Choi, Geun-Suk Park, Sung-Hyung Park, Young-Jin Park, Myoung-Jun Jang, Key-Min Lee, Hee-Goo Youn, Hi-Deok Lee, Ki-Seok Yoon, Joo-Hyoung Lee |
| Rok vydání: |
2002 |
| Předmět: |
|
| Zdroj: |
2001 6th International Symposium on Plasma- and Process-Induced Damage (IEEE Cat. No.01TH8538). |
| DOI: |
10.1109/ppid.2001.929994 |
| Popis: |
Until now, antenna ratio was considered one of the most important parameters for plasma induced damage, and tolerable antenna ratio is very important for circuit designers to guarantee high yield circuits. In this paper, the dependence of plasma induced damage on the gate area is characterized using novel test patterns. The test chip is fabricated using 0.15 /spl mu/m CMOS technology with low-k IMD material. The variation of gate current is used to detect the plasma induced damage. It is shown that the failure rates of transistor increase as the gate area in the transistor increases although the antenna ratio maintains constant. Therefore, to guarantee the reliability of the gate oxide and transistors, we propose that the dependence of plasma induced damage on gate area should be considered when defining the maximum tolerable antenna ratio. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
