Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design
| Autor: | Yong-Gee Ng, Kevin Zhang, Yih Wang, Pramod Kolar, Liqiong Wei, Fatih Hamzaoglu, Uddalak Bhattacharya |
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| Rok vydání: | 2011 |
| Předmět: |
Engineering
Bit cell Hardware_MEMORYSTRUCTURES business.industry Embedded memory Hardware_PERFORMANCEANDRELIABILITY Process variation Hardware and Architecture Low-power electronics Electronic engineering Static random-access memory Electrical and Electronic Engineering business Nanoscopic scale Scaling Software Voltage |
| Zdroj: | IEEE Design & Test of Computers. 28:22-31 |
| ISSN: | 0740-7475 |
| DOI: | 10.1109/mdt.2011.5 |
| Popis: | Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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