| Popis: |
With continuous development in the IC advanced technologies, physical verification is becoming increasingly more complex in the semiconductor manufacturing process. Currently, different regression patterns-based techniques are widely adopted in the design rules checking (DRC) verification. As complexity of design rules increases, limitations of those traditional techniques emerge such as focusing only on the rule final output, missing some of the underlying defects in the DRC Code, requiring many QA cycles for the rule deck to be released, and lacking well-defined measure of the DRC Coverage. This paper presents a new methodology in verifying the design rules checks, complementing the traditional Regression technique, through performing DRC rule deck line-by-line comparison with the regression layout patterns. This offers in-depth and quantitative analysis of all the DRC components, captures the possible defects in very early stages of the QA process, and reduces the time consumed in verification significantly compared to using just the traditional QA techniques. |
