An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping

Autor:	Yewei Zhang, Kejie Huang, Rui Xiao, Bo Wang, Yanfeng Xu, Jicong Fan, Haibin Shen
Rok vydání:	2022
Předmět:	Hardware and Architecture Electrical and Electronic Engineering Software
Zdroj:	IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:379-391
ISSN:	1557-9999 1063-8210
DOI:	10.1109/tvlsi.2022.3140395
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::486b92a7dc69ff289818d08fcf0e255b https://doi.org/10.1109/tvlsi.2022.3140395 Zobrazit plný text záznamu