Low‐latency digit‐serial dual basis multiplier for lightweight cryptosystems
| Autor: | Chiou-Yng Lee, Yun-Chi Yeh, Che Wun Chiou, Jim-Min Lin, Jeng-Shyang Pan |
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| Rok vydání: | 2017 |
| Předmět: |
Computational complexity theory
Computer Networks and Communications Computer science business.industry Cryptography 02 engineering and technology 020202 computer hardware & architecture Elliptic curve Finite field Dual basis 0202 electrical engineering electronic engineering information engineering Cryptosystem 020201 artificial intelligence & image processing Multiplier (economics) Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic business Time complexity Software Information Systems |
| Zdroj: | IET Information Security. 11:301-311 |
| ISSN: | 1751-8717 1751-8709 |
| DOI: | 10.1049/iet-ifs.2015.0336 |
| Popis: | Various cryptosystems, such as elliptic curve and pairing-based cryptosystems, in resource-constrained security applications rely on finite field multiplication. For applications such as these, a digit-serial multiplier has the potential features to achieve a trade-off between space and time complexities. The authors propose an efficient decomposition of the multiplication into four independent sub-multiplication units to facilitate parallel processing, which is additionally facilitated by the systolic structures of the sub-multiplication units. The proposed architecture uses a four-bit scheme to construct a novel processing element, instead of using only one bit as is currently used in similar multipliers. The results of the synthesis show that the proposed digit-serial dual basis multiplier eliminates up to 96% of the critical path delay. |
| Databáze: | OpenAIRE |
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