| Autor: |
David R. Hanson, Paul C. Parries, Norman Robson, Subramanian S. Iyer, T. Kirihata, Babar A. Khan, M. Wordeman, Geng Wang, J. Griesemer, Gregory J. Fredeman, R. Rajeevakumar, Hoki Kim, John W. Golz, Alberto Cestero |
| Rok vydání: |
2005 |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits. 40:1377-1387 |
| ISSN: |
0018-9200 |
| Popis: |
An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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