Abacus: a 1024 processor 8 ns SIMD array

Autor: Michael Bolotski, C. Vieri, Thomas F. Knight, Rajeevan Amirtharajah, T. Simon
Rok vydání: 2002
Předmět:
Zdroj: ARVLSI
DOI: 10.1109/arvlsi.1995.515609
Popis: Describes the Abacus machine at a number of levels. Presents the microarchitecture of the PE comprising the reconfigurable bit-parallel array, a set of arithmetic and communication primitives, details of the VLSI implementation, and system-level design issues of a high-speed SIMD array. The most concrete goal of the Abacus project was to design and build a machine that could be used by members of the MIT Artificial Intelligence Laboratory for real-time early vision processing. Along the way, we explored several architectural ideas.
Databáze: OpenAIRE