| Autor: |
Yipeng Wang, Junho Cho, Eugene Ho, Ma Shaojun, Asma Laraba, Yohan Frans, Daniel Wu, Kee Hian Tan, Wenfeng Zhang, Chi Fung Poon, Ying Cao, Parag Upadhyaya, Winson Lin |
| Rok vydání: |
2021 |
| Předmět: |
|
| Zdroj: |
VLSI Circuits |
| DOI: |
10.23919/vlsicircuits52068.2021.9492467 |
| Popis: |
This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12 data slicers and 2 error slicers. The quad-rate voltage-mode transmitter implements delay based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband LC PLL is distributed to eight transceiver channels. In each channel, an ILO generates eight-phase clocks that feed an 8-bit CMOS PI. The transceiver achieves |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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