Design of FPGA-based Architecture for an Analog Front-End in Broadband PLC
| Autor: | Alvaro Hernandez, Francisco Membibre, Ruben Nieto |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
business.industry
Computer science 020209 energy 020208 electrical & electronic engineering 02 engineering and technology Analog front-end Smart grid Modulation Gate array Broadband 0202 electrical engineering electronic engineering information engineering business Field-programmable gate array Computer hardware |
| Zdroj: | ETFA |
| DOI: | 10.1109/etfa.2019.8869166 |
| Popis: | Power-Line Communications have spread worldwide in recent years, mainly due to their increasing importance as a feasible alternative to provide broadband data access in certain domains, such as Smart Grids, Internet of Things or industrial environments in general, where the mains are available. Broadband PLC implies significant computational requirements, often related to multi-carrier modulations and high data rates that should be managed in parallel. Furthermore, these data rates also involve the necessity of specific analog front-ends (AFE), capable of tackling the corresponding high sampling frequencies in A/D and D/A converters. This work describes the design of an FPGA-based (Field-Programmable Gate Array) architecture, in charge of managing an ad-hoc AFE for broadband PLC. The proposal also implements a Filter-Bank Multi-Carrier (FBMC) modulation as medium access technique and a synchronism based on pilot sequences. A dedicated peripheral has been designed for that purpose, which has been integrated in a System-on-Chip (SoC). The proposal has been verified experimentally, validating the expected functionality. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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