SMT-SA: Simultaneous Multithreading in Systolic Arrays
| Autor: | Gil Shomron, Uri Weiser, Tal Horowitz |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Computer science
02 engineering and technology Energy consumption Parallel computing Grid Simultaneous multithreading Matrix multiplication 020202 computer hardware & architecture Convolution Instruction set Hardware and Architecture Multithreading 0202 electrical engineering electronic engineering information engineering Energy (signal processing) |
| Zdroj: | IEEE Computer Architecture Letters. 18:99-102 |
| ISSN: | 2473-2575 1556-6056 |
| DOI: | 10.1109/lca.2019.2924007 |
| Popis: | Systolic arrays (SAs) are highly parallel pipelined structures capable of executing various tasks such as matrix multiplication and convolution. They comprise a grid of usually homogeneous processing units (PUs) that are responsible for the multiply-accumulate (MAC) operations in the case of matrix multiplication. It is not rare for a PU input to be zero-valued, in which case the PU becomes idle and the array becomes underutilized. In this paper we consider a solution to employ the underutilized PUs via simultaneous multithreading (SMT). We explore the design space of a SMT-SA variant and evaluate its performance, area efficiency, and energy consumption. In addition, we suggest a tiling method to reduce area overheads. Our evaluation shows that a 4-thread FP16-based SMT-SA achieves speedups of up to 3.6× as compared to conventional SA, with 1.7× area overhead and negligible energy overhead. |
| Databáze: | OpenAIRE |
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