| Autor: |
K.C. Tu, Shou-Gwo Wuu, C.N. Pen, C.C. Wang, T. H. Hsieh, K. C. Huang, M. J Wang, C.Y. Pai, K.C. Tzeng, W. C. Chiang, C.Y. Tsai, L.C. Tran, Y.W. Chang, Chia-Shiung Tsai, Hau-Yu Lin, Chun-Yen Chang, H.Y. Hwang, H. C. Chu, Ching-Chun Wang, Y.W. Ting, Y.T. Hsieh, K.W. Chen |
| Rok vydání: |
2012 |
| Předmět: |
|
| Zdroj: |
Proceedings of Technical Program of 2012 VLSI Technology, System and Application. |
| DOI: |
10.1109/vlsi-tsa.2012.6210164 |
| Popis: |
A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitor's capacitance >10fF/cell and keep the low leakage (10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >330MHz. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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