Testable design of BiCMOS circuits for stuck-open fault detection using single patterns
| Autor: | S.M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, R. Rajsuman |
|---|---|
| Rok vydání: | 1995 |
| Předmět: |
Engineering
business.industry Design for testing Circuit design Hardware_PERFORMANCEANDRELIABILITY Integrated circuit design BiCMOS Fault (power engineering) Fault detection and isolation Charge sharing Electronic engineering Electrical and Electronic Engineering business Testability Hardware_LOGICDESIGN |
| Zdroj: | IEEE Journal of Solid-State Circuits. 30:855-863 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.400427 |
| Popis: | Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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