High-Speed Loop Unrolled Grain Architecture in Reconfigurable Hardware
| Autor: | Suman Sau, Rourab Paul, Paresh Baidya |
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| Rok vydání: | 2020 |
| Předmět: |
Coprocessor
Reduced instruction set computing business.industry Computer science Reconfigurable computing Software Application-specific integrated circuit Embedded system VHDL Hardware_INTEGRATEDCIRCUITS Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Throughput (business) computer Hardware_LOGICDESIGN computer.programming_language |
| Zdroj: | Advances in Intelligent Systems and Computing ISBN: 9789811514821 |
| DOI: | 10.1007/978-981-15-1483-8_15 |
| Popis: | Crypto core finds implementaions in software, Application Specific Integrated Circuit (ASIC), and Field Programmable Gate Array (FPGA). The crypto software programs achieve very less throughput, whereas ASIC implementations serve reasonably cost-effective design with efficient performance. In ASIC platform, once the design is implemented, it is not possible to alter those circuit connection, whereas FPGA is a flexible solution which can be reconfigured in the field. For huge number of gate applications, FPGA is cost-effective compared to ASIC and software implementation. This submission explores FPGA design spaces of Grain crypto hardware core. The article implements seven loop unrolled architectures which are implemented in Xilinx Zynq FPGA using VHDL language in Vivado Design Suit. The results show that three basic systems’ parameters such as resource usage, power consumption, and throughput of proposed implementation are satisfactorily optimized compared to existing literature. |
| Databáze: | OpenAIRE |
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