| Autor: |
J.E. Brewer, J. E. Demaris, L.C. Miller, D. Garde, I.H. Gilbert, J.F. Melia |
| Rok vydání: |
1994 |
| Předmět: |
|
| Zdroj: |
IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B. 17:310-317 |
| ISSN: |
1070-9894 |
| DOI: |
10.1109/96.311779 |
| Popis: |
A single-chip 120 MFLOP (peak) 26 million transistor digital processing subsystem with 512 kilobytes of on-chip SRAM has been developed. This general purpose 32-bit floating point Harvard architecture device, which incorporates sophisticated communication capabilities and at maximum throughput dissipates less than 2 W, can be used as a stand-alone processor or as a building block for both SIMD and MIMD processor arrays. This paper describes physical and functional features of the chip, and provides some discussion of how it can be applied. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
