| Popis: |
Grayscale lithography is a well-known technique for three dimensional structuring of a photo sensitive material. The 3D structuring of the photoresist is performed by a spatially variable exposure. Pixelated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. Within power semiconductor processing, grayscale techniques could beneficially be applied in different process steps. Several ideas come to mind for process simplification, alternative integration scheme and more, e.g. the realization of 3D resist patterns for implant applications in order to control the doping depth and profiles and their influence on device parameters. In order to make the grayscale process useful for manufacturing of semiconductor devices it is necessary to master and consider the inherent process variability. Lithographic simulation is used to optimize the sub-resolution photo-mask features and to predict the final resist shape and its variability. Device simulation for a DMOS device, used in our 130nm technology node, shows that the device performance would benefit from an attenuation of the implant dose in the center of the device, which could be achieved by creating a resist island with reduced resist thickness in the center of the drawn implant opening of the DMOS device. In order to achieve the desired target geometry of the implant resist mask, simulations with Sentaurus Lithography have been performed resulting in a suitable mask design and lithographic process. We will demonstrate the development of the grayscale litho-process based on the needs of an implant scheme that is going to be used for a DMOS device, with respect to process stability and achieved resist mask dimensions. |
