| Popis: |
This paper discusses a set of functions which are added to Verilog through its PLI interface that facilitates test and application of test programs to designs at the RT level. Using this package, not only enables a designer to apply test programs to RTL designs, but also takes advantage of RTL simulation of abstract HDL descriptions for speeding up test programs. The package proposed here eliminates the gap between design and test engineers by providing test facilities in the languages that designers are familiar with. |
