Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata

Autor:	Remy Chevallier, Weiwen Xu, Laurent Fribourg, Emmanuelle Encrenaz-Tiphene
Rok vydání:	2006
Předmět:	Correctness Computer engineering Asynchronous communication Computer science Memory architecture Parallel computing Formal methods Implementation Real-time operating system Asynchronous circuit Automaton Parametric statistics
Zdroj:	Lecture Notes in Computer Science ISBN: 9783540450269 FORMATS
DOI:	10.1007/11867340_9
Popis:	Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This allows us to check two different implementations of this architecture.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::0d5ad7278c35d765befe2a0b19c42106 https://doi.org/10.1007/11867340_9 Zobrazit plný text záznamu