A 23mW/lane 1.2–6.8Gb/s multi-standard transceiver in 28nm CMOS

Autor:	Wei Zhang, Mahmoud Reza Ahmadi, Heng Zhang, Mohammed Abdul-Latif, Tamer Ali, Seong-Ho Lee, Guansheng Li, Afshin Momtaz, Burak Catli, Zhi Huang, Duke Tran
Rok vydání:	2014
Předmět:	Phase-locked loop Engineering CMOS Power consumption business.industry Embedded system Transceiver XAUI business Computer hardware Power (physics) PCI Express Jitter
Zdroj:	A-SSCC
DOI:	10.1109/asscc.2014.7008871
Popis:	This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2–6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI. Power consumption per lane is 23mW at 0.9V for SATA3 at 6Gb/s, with an area of 0.265mm2 for a single-lane transceiver with PLL.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::0a7f15f777d888aedd2a9574f05467e2 https://doi.org/10.1109/asscc.2014.7008871 Zobrazit plný text záznamu