Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
| Autor: | Kathy Barla, G. Mannaert, Romain Ritzenthaler, Harold Dekkers, S. A. Chew, Hans Mertens, J. Geypen, Stefan Kubicek, Patrick Carolan, Adrian Chasin, Lars-Ake Ragnarsson, Tom Schram, Andriy Hikavyy, A. Dangol, Hugo Bender, Kurt Wostyn, Min-Soo Kim, Dan Mocuta, Naoto Horiguchi, Steven Demuynck, Katia Devriendt, T. Hopf, Erik Rosseel, Y. Kikuchi, N. Bosman, Eddy Kunnen |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Materials science Silicon business.industry Doping Transistor Nanowire chemistry.chemical_element Nanotechnology 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences law.invention Gallium arsenide chemistry.chemical_compound CMOS chemistry law Logic gate 0103 physical sciences Optoelectronics 0210 nano-technology business Metal gate |
| Zdroj: | 2016 IEEE International Electron Devices Meeting (IEDM). |
| Popis: | We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies. |
| Databáze: | OpenAIRE |
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