| Popis: |
In this paper, a time-area efficient hardware decoder of the (23, 12, 7) quadratic residue code, or Golay code, is presented. The key feature of this proposed algorithm lies in fast determination of error positions through the analysis on the weight of syndromes without large operations in finite fields. Comparing with the algorithm using one syndrome, the proposed algorithm is more suitable for the parallel hardware design by using two syndromes. Based on an Altera Cyclone II field-programmable gate array (FPGA) device (EP2C35F484C6), the area cost and the time delay of the complete system are reduced by up to 86.4% and 22.5%, respectively. Using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-@mm complementary metal-oxide-semiconductor (CMOS) standard cell library, the proposed decoder is 91.8% smaller and 8.3% faster. |
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