A 151-mm$^{2}$ 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology
| Autor: | Hong Ding, Yoshihiko Shindo, Kiyomi Naruke, Bo Lei, Hitoshi Shiga, T. Ogawa, Dana Lee, Junichi Sato, Eiichi Makino, Yuka Furuta, Dai Nakamura, Y. Kato, Go Shikata, Yoshinao Suzuki, Hiromitsu Komai, Yohji Watanabe, Alex Mak, T. Miwa, Rieko Tanaka, Manabu Sakai, M. Nakamichi, Takatoshi Minamoto, Gertjan Hemink, Kosuke Yanagidaira, T. Hara, Junji Musha, Brian Murphy, Yoshikazu Hosomura, Naoaki Kanagawa, Ayako Yuminaka, Kiyofumi Sakurai, Toshiaki Edahiro, Koichi Fukuda, Naoya Tokiwa, Koichi Kawakami, M. Higashitani, Makoto Iwai, Mai Muramoto, Yoshiyuki Matsunaga, Teruo Takagiwa, Manabu Watanabe, Osamu Nagao |
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| Rok vydání: | 2012 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 47:75-84 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2011.2164711 |
| Popis: | A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optimized peripheral circuit floor plan, are introduced. As a result, 151 mm2 die size with an excellent 79% cell area efficiency is achieved. Newly introduced precharge detect algorithm and smart precharge algorithm improve program throughput by 10%. 14 MB/s program throughput is obtained, which is comparable or even higher performance than NAND flash memories reported in the previous 30 nm technology generation. The proposed smart precharge algorithm reduces program operation current by 6%, and 25 mA operation current with 16 KB programming is achieved. Moreover, a high-speed asynchronous DDR interface is incorporated and 266 MB/s data transfer is achieved. |
| Databáze: | OpenAIRE |
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