| Autor: |
Jihoon Jeong, Francois Ibrahim Atallah, Daniel Yingling, Hoan Nguyen, Keith Bowman |
| Rok vydání: |
2018 |
| Předmět: |
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| Zdroj: |
IEEE Solid-State Circuits Letters. 1:225-228 |
| ISSN: |
2573-9603 |
| DOI: |
10.1109/lssc.2019.2911885 |
| Popis: |
A 7-nm register file (RF) with a 16-transistor (16T) 3-read and 3-write (3R3W) bitcell double pump or time multiplexes the read and write access ports twice per clock cycle to achieve 6-read and 6-write (6R6W) operations per cycle for high-bandwidth (BW) on-die memory in high-performance machine learning and CPU processors. From silicon test-chip measurements at 0.9 V, the double-pumped (DP) 6R6W RF trades off a 19% lower maximum clock frequency ( $F_{\mathrm{ MAX}}$ ) for $2\times $ the number of read and write operations per cycle, resulting in a 62% higher memory BW compared to a conventional single-access (SA) 3R3W RF. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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