On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM
| Autor: | Stanley E. Schuster, R.L. Franch, B.A. Chappell, Terry I. Chappell |
|---|---|
| Rok vydání: | 1992 |
| Předmět: |
Digital electronics
Engineering Hardware_MEMORYSTRUCTURES business.industry Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Emitter-coupled logic Chip law.invention Voltage-controlled oscillator CMOS Built-in self-test law Hardware_INTEGRATEDCIRCUITS Electronic engineering Static random-access memory Electrical and Electronic Engineering business |
| Zdroj: | IEEE Journal of Solid-State Circuits. 27:1073-1079 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.142604 |
| Popis: | On-chip test circuitry that provides 8-b-deep emitter-coupled logic (ECL) level patterns to 12 input pads of a 512-kb CMOS ECL static RAM (SRAM) at cycle times as fast as 1.4 ns has been built in a 0.8- mu m CMOS technology with L/sub eff/=0.5 mu m. A unique approach for synchronizing the input signals to the chip-select signal in order to provide an optimum setup time and data-valid windows as the operating frequency changes is described. Measured results and extensive simulation demonstrate the stability of the on-chip test circuitry for cycle times of 1.4-50 ns. The on-chip test circuitry makes it possible to test the SRAM chip at its pipelined cycle time. In addition, the speed of the on-chip test circuitry will track future technology improvements, making it possible to generate test patterns as SRAM performance continues to improve. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|