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Test compression has become a requirement for many designs to meet the required test quality levels in reasonable test times and with acceptable test cost. This session will cover some of the tradeoffs and options available from the broad spectrum of test compression solutions. The first talk will address the difficulty when testing large numbers of logic blocks and processor cores of maintaining high test quality without a requisite increase in test cost stemming from the need to allocate substantially more pins for digital test. Simply adding more chip-level pins for testing conflicts with packaging constraints and can potentially undermine other cost-saving techniques that rely on utilizing fewer pins such as multi-site testing. What is needed instead is a DFT strategy optimized for complex SOC designs that use multicore processors-a strategy in which the architecture and automation elements work in tandem to lower test cost without compromising test quality or significantly increasing automatic test pattern generation (ATPG) runtime. This presentation highlights an optimized DFT architecture, referred to as “shared I/O” of DFTMAX, a synthesis-based test solution that has been used successfully in multicore processor designs as well as complex SOC designs. Using this approach, they were able to reduce scan test pins significantly with similar or even less ATPG patterns, without compromising test coverage, and achieve over 2X reduction in wafer level scan test time. The second talk will present many DFT techniques to reduce test time and improve coverage in the context of core wrapping. Some of these methods include using external scan chains with separate compression logic inside each place-and-route block instead of having ‘chip-top’ scan compression logic for all external scan chains from different place-and-route. In addition, some tradeoffs of using dynamic launch-on-shift/launch-on-capture (LOS/LOC) instead of static will be covered. Some other methods will be covered for preventing decompressor logic from feeding X'es during launch-on-shift test patterns and the benefits of control test-points to reduce ATPG vector counts. The final presentation will cover various methodologies for reducing the test data volume on different chips. Some work to achieve a higher compression ratio in the future will also be discussed. As with any good engineering solution, there are some constraints and tradeoffs that also need to be considered with those choices. |
