| Autor: |
Guelton, Serge, Irigoin, François, Keryell, Ronan |
| Přispěvatelé: |
Département informatique (INFO), Université européenne de Bretagne - European University of Brittany (UEB)-Télécom Bretagne-Institut Mines-Télécom [Paris] (IMT), Centre de Recherche en Informatique (CRI), MINES ParisTech - École nationale supérieure des mines de Paris, Université Paris sciences et lettres (PSL)-Université Paris sciences et lettres (PSL), HPC PROJECT, HPC Project |
| Jazyk: |
angličtina |
| Rok vydání: |
2011 |
| Předmět: |
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| Popis: |
Hardware accelerators, such as fpga boards or gpu, are an interesting alternative or a valuable complement to classic multi-core processors for computational-intensive software. However it proves to be both costly and difficult to use legacy applications with these new heterogeneous targets. In particular, existing compilers are generally targeted toward code generation for sequential processors and lack the required abstractions and transformations for automatic code generation and code re-targeting for heterogeneous targets. The goal of this article is to introduce a set of high-level code transformations based on an abstraction of existing hardware architectures that make it possible to build compilers specific to a target using a shared infrastructure. These transformations have been used to build two completely automatic compilers for an fpga - based embedded processor and an nvidia gpu. The latter is validated on several representative digital signal processing kernels. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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