| Autor: |
Renukaswamy, Pratap Tumkur, Vaesen, Kristof, Markulic, Nereo, Craninckx, Jan |
| Zdroj: |
IEEE Journal of Solid-State Circuits; 2024, Vol. 59 Issue: 6 p1684-1696, 13p |
| Abstrakt: |
A 16-GHz charge-pump phase-locked loop (CP-PLL) for a robust duty-cycled frequency-modulated continuous-wave (FMCW) radar chirp generation is presented. A duty-cycling (DC) scheme is introduced to reduce the overall power consumption. To enable fast startup and fast locking, a two-point modulated CP-PLL frequency modulator is designed. To enable the two-point gain mismatch calibration a time-domain sign extraction technique is explored. The 16-GHz chirp generator achieves a 29.3-MHz/ $\mu \text{s}$ chirp slope with 41-kHz rms-frequency error for 1.5-GHz chirp bandwidth while consuming 16.5-mW power. The modulator can be used in a heavily duty-cycled regime, due to its robust below 1- $\mu \text{s}$ phase-locked loop (PLL) phase/frequency lock time. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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