| Abstrakt: |
With the advancements in digital communication systems, security is one of the essential components of real-time communication systems. Packet classification is one of the most important networking tasks that helps to prevent hacking and unintended effects on connected devices. The slow processing speed of the router and other devices connected to it is an issue with real-time packet classification implementation. In this study, a brand-new architecture for packet classification in routers is put forth. The suggested design is capable of operating at high frequencies, which can satisfy the real-time requirements for networking applications. The proposed design uses low-area components with enhanced speed capabilities for higher energy efficiency. The design is implemented in both application-specific integrated circuits (ASICs) and field programmable gate array (FPGA) logic devices to validate the output. FPGA families, including the Virtex-4, 5, and 7 families, are used for synthesising in Xilinx software. |
