| Autor: |
Borland, John Ogawa |
| Zdroj: |
IEEE Electron Devices Magazine; December 2023, Vol. 1 Issue: 3 p9-21, 13p |
| Abstrakt: |
Selective epitaxial growth (SEG) is one of the key front end-of-line (FEOL) process technologies today that has been used in CMOS device manufacturing for 20 years. Intel introduced the use of SEG in the 90-nm node planar CMOS for the pMOS sources/drain (S/D) stressor back in 2003. It combined elevated S/D technology with recess etching S/D junction formation and silicon germanium (SiGe) for local channel strain. However, the first reported publication on SEG goes back 61 years to an article reported by Joyce and Baldrey of Texas Instruments in Nature in 1962 [1]. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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