| Abstrakt: |
This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter(ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture.Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparatorsare identified on their suitability of the design for ADCs. These are effective in the area and bit resolution.The overview includes bit resolution, area, power dissipation, bandwidth and offset noise considerationfor high-speed flash ADC design. A MUX-based two-step half flash architecture is consideredfor applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advancedcomparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are alsoreviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer. |
