| Abstrakt: |
Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere. Due to ever increasing growth of the digital systems especially in the wireless communication, the Digital PLL (DPLL) has been developed to overcome the disadvantages of analog techniques such as large noise, power hungry, parameter sensitivity etc. Besides DPLL provides faster lock-in time, better testability, stability and portability over different process. The most of the resources available discussed about the theoretical model of the DPLL which is not synthesizable, that’s why a model is presented here keeping in mind that must be fully digital and synthesizable. The proposed PLL structure is fully digital, has the design flexibility with reduced hardware, low power consumption and higher power efficiency. |
