25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
| Autor: | Oh, Tae-Young, Chung, Hoeju, Cho, Young-Chul, Ryu, Jang-Woo, Lee, Kiwon, Lee, Changyoung, Lee, Jin-Il, Kim, Hyoung-Joo, Jang, Min Soo, Han, Gong-Heum, Kim, Kihan, Moon, Daesik, Bae, Seungjun, Park, Joon-Young, Ha, Kyung-Soo, Lee, Jaewoong, Doo, Su-Yeon, Shin, Jung-Bum, Shin, Chang-Ho, Oh, Kiseok |
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| Zdroj: | 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); 2014, p430-431, 2p |
| Databáze: | Complementary Index |
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