A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter.
| Autor: | Matsuura, T., Nara, T., Komatsu, T., Imaizumi, E., Horita, R., Katsu, H., Suzumura, S., Sato, K. |
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| Zdroj: | IEEE Journal of Solid-State Circuits; 1998, Vol. 33 Issue 11, p1840-1850, 11p |
| Databáze: | Complementary Index |
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