A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.
| Autor: | Kirihata, T., Gall, M., Hosokawa, K., Dortu, J.-M., Hing Wong, Pfefferi, P., Ji, B.L., Weinfurtner, O., DeBrosse, J.K., Terletzki, H., Selz, M., Ellis, W., Wordeman, M.R., Kiehl, O. |
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| Zdroj: | IEEE Journal of Solid-State Circuits; 1998, Vol. 33 Issue 11, p1711-1719, 9p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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