A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture.
| Autor: | Chappell, T.I., Chappell, B.A., Schuster, S.E., Allan, J.W., Klepner, S.P., Joshi, R.V., Franch, R.L. |
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| Zdroj: | IEEE Journal of Solid-State Circuits; 1991, Vol. 26 Issue 11, p1577-1585, 9p |
| Databáze: | Complementary Index |
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