A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.
| Autor: | Higeta, K., Usami, M., Ohayashi, M., Fujimura, Y., Nishiyama, M., Isomura, S., Yamaguchi, K., Idei, Y., Nambu, H., Ohhata, K., Hanta, N. |
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| Zdroj: | Proceedings of Bipolar/Bicmos Circuits & Technology Meeting; 1995, p47-50, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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