| Autor: |
Akarvardar, K., Rodgers, M., Kaushik, V., Johnson, C.S., Ok, I., Ang, K.-W., Stamper, H., Bennett, S., Franca, D., Rao, M., Gausepohl, S., Hobbs, C., Kirsch, P., Jammy, R. |
| Zdroj: |
Proceedings of Technical Program of 2012 VLSI Technology, System & Application; 1/ 1/2012, p1-2, 2p |
| Abstrakt: |
Low temperature (T ≤ 480C after gate stack) DS Metal S/D GAA PFETs were fabricated and benchmarked to devices with S/D activation anneal (SDAA). It is shown that when DS implantation precedes gate spacer formation, devices without SDAA have higher peak Gm and IDsat, however also higher Ioff than their counterparts with SDAA. Fabricated low-thermal-budget GAA PFETs with TiN/HfO2 gate and NiPtSi S/D achieve IDsat = 0.8 mA/um and Ion/Ioff > 2000 for VGS = −1.5 V, VDS = −1 V, and 100 nm nanowire length. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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