16×16 bit parallel multiplier based on 6 K gate array with 0.3 μm AlGaAs/GaAs quantum well transistors.
| Autor: | Thiede, A., Berroth, M., Hurm, V., Nowotny, U., Seibel, J., Gotzeina, W., Sedler, M., Raynor, B., Koehler, K., Hofmann, P., Huelsmann, A., Kaufel, G., Schneider, J. |
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| Zdroj: | Electronics Letters (Institution of Engineering & Technology); 05/21/1992, Vol. 28 Issue 11, p1005-1007, 3p |
| Databáze: | Complementary Index |
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