Effective interconnect networks design in CMOS 45 nm circuits to joint reductions of XT and delay for transmission of very high speed signals.
| Autor: | de Rivaz, S., Farcy, A., Deschacht, D., Lacrevaz, T., Flechet, B. |
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| Zdroj: | 2010 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS); 2010, p1-4, 4p |
| Databáze: | Complementary Index |
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