A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.
| Autor: | Jacunski, M., Anand, D., Busch, R., Fifield, J., Lanahan, M., Lane, P., Paparelli, A., Pomichter, G., Pontius, D., Roberge, M., Sliva, S. |
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| Zdroj: | 2010 IEEE Custom Integrated Circuits Conference (CICC); 2010, p1-4, 4p |
| Databáze: | Complementary Index |
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