How circuit analysis and yield optimization can be used to detect circuit limitations before silicon results.
| Autor: | Roma, C., Daglio, P., De Sandre, G., Pasotti, M., Poles, M. |
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| Zdroj: | Sixth international Symposium on Quality Electronic Design (ISQED'05); 2005, p107-112, 6p |
| Databáze: | Complementary Index |
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