A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%.
| Autor: | Yokoyama, Y., Itoh, N., Katayama, M., Takashima, K., Akasaki, H., Kaneda, M., Ueda, T., Tanaka, Y., Yamasaki, E., Todokoro, M., Toriyama, K., Miki, H., Yagyu, M., Kobayashi, T., Miyaoka, S., Tamba, N. |
|---|---|
| Zdroj: | Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044); 2000, p279-282, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|