Save Those Watts With A Power-Aware Design Flow For SoCs.

Autor:	Bhatnagar, Mohit, Erickson, Jack, Iyer, Anand, McCrorie, Pete
Předmět:	INTEGRATED circuit design ELECTRONIC circuit design POWER resources ELECTRONIC systems APPLICATION-specific integrated circuits ENERGY consumption INDUSTRIAL management ELECTRONIC circuits MICROELECTRONICS
Zdroj:	Electronic Design; 7/6/2006, Vol. 54 Issue 15, p63-70, 6p, 5 Diagrams, 1 Chart
Abstrakt:	The article discusses the value of a design flow for system-on-a-chip (SoCS) to achieve a more efficient power consumption. One means of conserving power in an SoCS is to design with several power domains. Some domains can be kept running at a lower supply voltage. Also, the power of a domain can be switched off when it is not being used. Other power-management techniques are hierarchical clock gating, low-power clock-tree synthesis, leakage optimization methods, and global concurrent optimization of timing, area and power.
Databáze:	Complementary Index
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