| Autor: |
Xiong, Botao, Fan, Sheng, He, Xintong, Zhou, Zezhao, Yang, Runhua, Li, Sicun, Shen, Rensheng, Chang, Yuchun |
| Zdroj: |
International Journal of Circuit Theory & Applications; Apr2024, Vol. 52 Issue 4, p1864-1871, 8p |
| Abstrakt: |
The challenge in designing the high‐performance field‐programmable gate array (FPGA)‐based convolution accelerator is to take full advantage of the on‐chip computing resources. The reported CNN accelerators always exhaust the on‐chip DSPs and leave other computing resources under‐utilized. Hence, this brief presents a novel convolution acceleration core based on the small logarithmic floating‐point (SLFP) format, which results in three contributions. (1) The SLFP<3,5> multiplier is only implemented with 13× LUT6s and operates at 650 MHz with the aid of the carry chain, which provides sufficient accuracy for most CNNs. In addition, a similar structure can be used to implement a SLFP<3,5> divider. (2) The DSPs in the TWO24 SIMD mode are cascaded to implement a 9‐input adder tree. The sum of the multiples of 9× elements (e.g., 18×, 27×) is easily obtained by configuring the last DSP in the 9‐input adder tree in the accumulation mode, which can support more kernels (e.g., 5×5, 128×1×1) with a high utilization rate (≈90%). (3) The convolution core based on the SLFP format only uses 654× LUT6s and 7× DSPs to achieve 1300 MOPS, 433 MOPS, and 81 MOPS for 3×3, 5×5, and 128×1×1 kernel, respectively. In summary, the proposed convolution accelerator not only balances the resource usage of LUT6s and DSPs but also quantizes most CNN models using several simple scaling operations instead of a computing‐intensive retraining algorithm because the distribution of SLFP numbers is very similar to FP32 numbers. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
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