| Abstrakt: |
A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1 / f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 n m CMOS technology. The cascaded receiver achieves a conversion-gain from 26 d B to 36 d B , a double-sideband noise-figure (NFDSB) from 1.4 d B to 3.9 d B , S 11 < − 10 d B and an IIP3 from − 7.5 d Bm to − 10.5 d Bm , over the RF operating band from 0.4 G Hz to 12 G Hz. The stacked receiver achieves a conversion-gain from 34.5 d B to 36 d B , a NFDSB from 4.6 d B to 6.2 d B , S 11 < − 10 d B , and an IIP3 from − 21 d Bm to − 17.5 d Bm , over the RF operating band from 2.2 G Hz to 3.2 G Hz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage. [ABSTRACT FROM AUTHOR] |
