| Abstrakt: |
Moving from homogeneous to heterogeneous architectures offers performance, size, weight, and power advantages, which are especially important for embedded solutions. However, the development of parallel software for heterogeneous computing systems is a rather difficult task due to the requirements of high performance, easy programmability, and scalability. The paper investigates the efficiency of parallel-pipeline processing of video information in multicore heterogeneous systems on a chip (SoC). A mathematical model of the used structures is described and the criteria for efficiently processing video data are formulated, based on which the target function is built. The typical scheme for parallel-pipeline processing of video data using various streaming video processing accelerators (DSP, GPU, ISP, VDP, VPU, etc.) is presented. A scheme for parallel-pipeline processing of video data on a heterogeneous 1892VM248 SoC is developed. A technique for efficient parallel-pipeline video information processing in heterogeneous computing SoCs, including a software stack consisting of an operating system level, a programming technology level, and an application level, is proposed. A comparative analysis of the most common programming technologies for heterogeneous SoCs, such as OpenCL, OpenMP, MPI, and OpenAMP, is carried out. The results of the analysis show that, depending on the purpose of the end device, two programming paradigms should be used: based on OpenCL technology (for embedded systems) and MPI technology (for intercore and interprocessor interactions). The results of parallel-pipeline processing in the face recognition problem confirms the effectiveness of the chosen solutions. [ABSTRACT FROM AUTHOR] |
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