| Autor: |
Wang, Perry H., collins, Jamison. D., Wang, Hong, Kim Bil, Ooogkeun, Kal-ming Chan, Greene, Aamir B. Yunus, Terry Sych, Moore, Stephen E., Shen, John P. |
| Předmět: |
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| Zdroj: |
IEEE Micro; Nov/Dec2004, Vol. 24 Issue 6, p74-82, 9p |
| Abstrakt: |
This article focuses on helper threads via virtual multithreading. These speculative threads attempt to trigger future cache miss events far enough in advance of access by the main thread to avoid the memory miss latency. As a special prefetching mechanism, helper threading targets load instructions that have been difficult to handle via traditional prefetching, such as loads that do not exhibit predictable access patterns and chains of dependent loads. A speculative thread occupies a hardware thread context until the speculative thread executes all instructions in the slice. Speculative threads must not update the architectural state, for example, by executing a store instruction. By the time the main thread reaches T3, the data is already in the cache. The evaluation of helper threading in both academic and industry research has mostly been based on simulation. Questions remain as to the effectiveness of this technique in practice. The authors therefore developed a new mechanism that prototypes and evaluates a helper thread prefetching technique on real hardware, demonstrating this mechanism on an Itanium 2 processor. |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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