| Autor: |
Jin, Jin, Wu, Jianhui, Castello, Rinaldo, Manstretta, Danilo |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Jul2022, Vol. 57 Issue 7, p1957-1967, 11p |
| Abstrakt: |
This work reports on a low-intermediate frequency (IF) voltage-mode receiver front-end for Internet-of-Things (IoT) applications. Design and noise analysis of an unbalanced gate-boosted common-gate low-noise amplifier (LNA) is presented, showing 50% lower power dissipation compared with the conventional balanced topology. Improved linearity is achieved thanks to channel-selection, consisting of two complex poles centered at 2 MHz IF. The first complex pole is embedded in the passive down-conversion mixer for improved frequency selectivity in front of the baseband voltage amplifier. Built in a 28-nm CMOS process, the proposed front-end occupies an active area of 0.175 mm2, it is supplied with 1 V and consumes only 400 $\mu \text{W}$ , while showing a minimum noise figure (NF) of 6.8 dB and an out-of-band (OOB) IIP3 of −0.35 dBm. The performance meets Bluetooth low-energy (BLE) requirements and is competitive with other sub-mW receivers. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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