| Autor: |
Takayanagi, Toshinari, Shin, Jinuk Luke, Petrick, Bruce, Su, Jeffrey Y., Levy, Howard, Ha Pham, Jinseung Son, Moon, Nathan, Bistry, Dina, Nair, Umesh, Singh, Mandeep, Mathur, Vikas, Leon, Ana Sonia |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Jan2005, Vol. 40 Issue 1, p7-18, 12p, 16 Black and White Photographs, 16 Diagrams, 1 Chart, 5 Graphs |
| Abstrakt: |
A dual-core 64-bit microprocessor optimized for compute-dense systems such as rack-mount and blade servers for network computing was developed. The chip consists of two Ultra- SPARC II cores, each with its own 512 kB L2 cache, a DDR-1 memory controller, and symmetric multiprocessor bus (JBus) controllers. The 206-mm² die is fabricated in 0.13-µm CMOS technology with seven layers of Cu and a low-k dielectric. The chip offers a highly efficient performance-per-watt ratio with a typical power dissipation of 23 W at 1.3 V and 1.2 GHz. A short design cycle was achieved by leveraging existing designs wherever possible and developing effective design methodologies and flows. Significant design challenges faced by this project are described. These include deep-submicron design issues, such as negative bias temperature instability (NB TI), leakage, coupling noise, intra-die process variation, and electromigration (EM). A second important design challenge was implementing a high-performance L2 cache subsystem with a short four-cycle core-to-L2 latency including ECC. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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